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| CXL1511M CCD Delay Line for PAL For the availability of this product, please contact the sales office. Description The CXL1511M is an IC developed for use in conjunction with Y/C signal processing ICs for PAL. This CCD delay line provides the comb filter output for eliminating the chrominance signal cross talk and 1H delay output for luminance signals. Features * Single power supply (5V) * Built-in triplex progression PLL circuit * Comb filter characteristics selectable * Delay time for 1H delay output selectable * Built-in peripheral circuits * Positive phase signal input, positive phase signal output Functions * Comb filter output * 1H delay output for luminance signal * Clock driver * Autobias circuit * Input clamp circuit (for luminance signals) * Center bias circuit (for chrominance signals) * Sample-and-hold circuit * Triplex progression PLL circuit * Luminance signal delay time/comb filter characteristics selection circuit * Clock buffer output circuit Absolute Maximum Ratings (Ta = 25C) * Supply voltage VDD +6 V * Operating temperature Topr -10 to +60 C * Storage temperature Tstg -55 to +150 C * Allowable power dissipation PD 500 mW Recommended Operating Voltage (Ta = 25C) VDD 5V 5% Structure CMOS-CCD 24 pin SOP (Plastic) Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E95224-ST CXL1511M Recommended Clock Conditions (Ta = 25C) * Input clock amplitude VCLK 0.3Vp-p to 1.0Vp-p (0.5Vp-p Typ.) * Clock frequency fCLK 4.433619MHz * Input clock waveform sine wave Input Signal Amplitude Vsig 350mVp-p (Typ.), 575mVp-p (Max.) Block Diagram and Pin Configuration (Top View) PCOUT C-OUT VCOIN CONT AB-C AB-P (NC) (NC) (NC) Vss 24 23 22 21 20 19 18 17 16 15 14 13 PLL fsc buffer Selector Timing D Output circuit (S/H) Autobias circuit (C) 1H/2H + D Autobias circuit (Y) Driver 1 Driver 2 Bias circuit Bias circuit Clamp circuit 1H Output circuit (S/H) 1 2 3 4 5 6 7 8 9 10 11 12 (NC) (NC) VDD C-IN1 (NC) (NC) Y-IN Vss Y-OUT C-IN2 -2- (NC) CLK Vss fsc CXL1511M SOP 24pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Symbol VSS C-IN1 VDD C-IN2 (NC) (NC) Y-IN (NC) Y-OUT (NC) (NC) CLK VSS VCOIN PCOUT (NC) (NC) (NC) AB-P fsc AB-C CONT C-OUT VSS I/O -- I -- I -- -- I -- O -- -- I -- I O -- -- -- O O O I O -- Clock input GND VCO input Phase comparator output -- -- -- Autobias output (P) fsc buffer output Autobias output (C) Control input Chrominance signal output GND GND Chrominance signal input 1 Power supply Chrominance signal input 2 -- -- Luminance signal input -- Luminance signal output -- -- Description -3- CXL1511M Description of Functions The CXL1511M enables the chrominance comb filter characteristics and luminance signal delay time to be selected in the control input state. CONT L H Mode (typical example) PAL/GBI 4.43NTSC Chrominance comb filter chracteristics 2H (1702.5bit) 1H (844.5bit) Luminance signal delay time (number of CCD bits) 1H (848.5bit) 1H (842.5bit) CONT Input Level L/H L H Min. -- 2.0 Typ. 0 5.0 Max. 0.5 6.0 Unit V * fsc Output Pin The buffer output of the clock input from the CLK pin is provided at the fsc output pin. Since a pull-up resistor is contained inside the IC, the supply voltage is produced during open, and the output is stopped. Connect a 2.2k pull-down resistor when the fsc output is to be used. fsc fsc VDD 2.2k -4- CXL1511M Electrical Characteristics (Ta = 25C, VDD = 5V, fCLK = 4.433619MHz, VCLK = 500mVp-p sine wave) See electrical Characteristics Measurement Circuit Item Supply current Symbol IDD1 IDD2 Measurement condition 1 -- b b SW condition 2 b b 3 b b 4 a a 5 a b 6 7 8 Min. Typ. Max. Unit NOTE a ---- a ---- 35 50 mA 1 Chrominance Signal Characteristics (No signals input to Y-IN) Item Symbol Measurement condition 1 a (See Note 2) a a a a (See Note 4) a a (See Note 5) 50% white video signal (See Note 7) a a a b b a SW condition 2 a a a a a a a a a a b b b 3 b b b b b b b b b b b b 4 a a a a a a a a a a a a 5 6 7 b b b b b b b b d d b b a -- 260 -- ns 8 52 56 dB 6 -40 -25 dB 5 -0.3 -2 Min. Typ. Max. Unit NOTE Low GLC1 frequency GLC2 gain Frequency response Linearity FC1 FC2 LIC1 LIC2 --a --a --a --a --a --a --a --a --a --a --a --a 0 2 dB 2 (See Note 3) -2.7 -1.7 0 dB 3 0 0.3 dB 4 Comb CCD1 depth min. CCD2 gain SNC1 SN ratio Coupling level Delay time SNC2 CPC1 CPC2 DC 10 50 mVrms 7 (See Note 8) b----a -5- CXL1511M Low GLY1 frequency GLY2 gain Frequency FY1 response FY2 Differential DGY1 gain DGY2 Differential DPY1 Phase DPY2 LNY1 Linearity LNY2 SNY1 SN ratio Coupling level SNY2 CPY1 CPY2 a-- a-- a-- a-- a-- a-- a-- a-- a-- a-- a-- a-- b-- b-- -2 0 2 dB 2 (See Note 3) 5-step staircase wave 5-step staircase wave (See Note 10) 50% white video signal (See Note 7) -6- CXL1511M Note 1. This is the IC's supply current value when no signals are input. 2. This is the C-OUT and Y-OUT pin output gain when 500mVp-p sine waves are input to C-IN1, C-IN2 and Y-IN. (Example of calculation) GLC1 = 20 log C-OUT pin output voltage (mVp-p) [dB] 500 (mVp-p) Input signal frequency GLC1 (2H) GLC2 (1H) GLY1, GLY2 : 203.126kHz : 204.750kHz : 200kHz 3. This indicates the difference in the C-OUT and Y-OUT pin output gain when 200mVp-p low- and highfrequency sine waves are input to C-IN1, C-IN2 and Y-IN. Set the input bias (Vbias) to 2.0V when measuring the luminance signal characteristics (GLY1, GLY2, GHY1, GHY2). (Example of calculation) FC1 = 20 log C-OUT pin output voltage (high frequency) (mVp-p) [dB] C-OUT pin output voltage (low frequency) (mVp-p) Input signal frequency (low frequency) see Note 2 Input signal frequency (high frequency) Chrominance signal (2H) : 4.429712MHz Chrominance signal (1H) : 4.425744MHz Luminance system : 4.43MHz 4. Calculate with the gain applying when 200mVp-p and 500mVp-p sine waves (see Note 2 for the frequencies) are input to C-IN1 and C-IN2. (Example of calculation) Output voltage with 500mVp-p input (mVp-p) 500mVp-p Output voltage with 200mVp-p input (mVp-p) 200mVp-p LIC1 = 20 log [dB] -7- CXL1511M 5. Measure the difference of the C-OUT output gain when 500mVp-p sine waves have been input to C-IN1 and C-IN2 at the following frequencies. Input signal frequency fp 4.429712MHz 4.425744MHz fN 4.425806MHz 4.417869MHz CCD1 CCD2 The frequency response for the outputs at fp and fN are shown in the figure below. Gain fN fp Frequency 6. Using the BPF 100kHz to 5MHz in the Sub Carrier Trap mode, measure the SN ratio on the video noise meter when the 50% white video signal shown in the figure below is input. 178mV 321mV 143mV 7. Measure the internal clock component (3fsc: 13.300856MHz component) when no signals are input. 8. Measure the delay time of the C-OUT output when the C-IN1 signal is input. -8- CXL1511M 9. On the vector scope, measure the differential gain and differential phase when the 5-step staircase wave shown in the figure below is input. 143mV 357mV 500mV 143mV 10. Input the 5-step staircase wave only for the luminance signal shown in the figure below, and measure the Y-OUT luminance level (Y) and SYNC level (S). (Example of calculation) LNY1 = 500mV Y 357mV S (mV) x 100 Y (mV) S 143mV -9- Electrical Characteristics Measurement Circuit 5V 1k a 0.1 1k 0.1 0.1 0.1 82k SW4 b 24 23 22 20 21 16 17 15 14 19 18 13 - 10 - 2 3 7 11 4 8 10 5 6 9 12 3.3 1000P a b 1k Vbias 1M SW5 0.01 5V 1k a SW6 b SW7 a Oscilloscope b Spectrum analyzer c LPF d BPF Vector scope Noise meter 1 Signal generator a SW1 b 0.01 a SW2 b 0.01 a SW3 b 0.1 A 5V CXL1511M CLK fsc (4.433619MHz) 0.5Vp-p sine wave Application Circuit 5V 1k C-OUT CONT1 (0/5V) fsc out When Pin 20 (fsc) output is used (connect to VDD when not used) 0.1 1k 0.1 0.1 0.1 24 23 22 20 21 16 17 15 14 19 18 13 2.2k 82k CXL1511M 5V 1 2 3 7 4 8 10 5 6 9 11 12 1k Y-OUT - 11 - 3.3 1000P 1M 5V C-IN1 0.01 0.01 C-IN2 0.01 Y-IN 0.1 CLK fsc (4.433619MHz) 0.5Vp-p sine wave CXL1511M Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. CXL1511M Example of Representative Characteristics Low frequency gain vs. Supply voltage 2 -1 Frequency response vs. Supply voltage Low frequency gain [dB] 1 Frequency response [dB] 0 -2 -1 -2 4.75 5 Supply voltage [V] 5.25 -3 4.75 5 Supply voltage [V] 5.25 Comb depth vs. Supply voltage -30 0.3 Chrominance linearity vs. Supply voltage 0.2 Chrominance linearity [dB] 5 Supply voltage [V] 5.25 Comb depth [dB] 0.1 -35 0 -0.1 -0.2 -40 4.75 -0.3 4.75 5 Supply voltage [V] 5.25 Differential gain vs. Supply voltage 5 5 Differential phase vs. Supply voltage 4 4 3 Differential phase [degree] 5 Supply voltage [V] 5.25 Differential gain [%] 3 2 2 1 1 0 4.75 0 4.75 5 Supply voltage [V] 5.25 - 12 - CXL1511M Low frequency gain vs. Ambient temperature 2 Frequency response vs. Ambient temperature -1 Low frequency gain [dB] 1 0 Frequency response [dB] 0 10 20 30 40 Ambient temperature [C] 50 60 -2 -1 -2 -10 -3 -10 0 10 20 30 40 Ambient temperature [C] 50 60 Comb depth vs. Ambient temperature -30 Chrominance linearity vs. Ambient temperature 2 Chrominance linearity [dB] 0 10 20 30 40 50 60 1 Comb depth [dB] -35 0 -1 -40 -10 -2 -10 0 10 20 30 40 Ambient temperature [C] 50 60 Ambient temperature [C] Differential gain vs. Ambient temperature Differential phase vs. Ambient temperature 2 Differential phase [degree] -10 0 10 20 30 40 Ambient temperature [C] 50 60 4 4 Differential gain [%] 2 0 0 -10 0 10 20 30 40 Ambient temperature [C] 50 60 - 13 - CXL1511M Package Outline Unit: mm 24PIN SOP (PLASTIC) + 0.4 15.0 - 0.1 24 13 + 0.4 1.85 - 0.15 0.15 + 0.3 5.3 - 0.1 7.9 0.4 + 0.2 0.1 - 0.05 0.45 0.1 1.27 + 0.1 0.2 - 0.05 0.12 M PACKAGE STRUCTURE MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SOP-24P-L01 SOP024-P-0300-A LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY/PHENOL RESIN SOLDER PLATING COPPER ALLOY / 42ALLOY 0.3g - 14 - 0.5 0.2 1 12 6.9 |
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